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Reset and Reset Configuration
A simple generic interrupt controller is implemented using a CPLD device. The interrupt
controller is implemented as an interrupt register and an interrupt mask register. The
interrupt controller has its’ own dedicated chip-select line (CS3). A simple priority scheme
is devised to prioritize the interrupts from different slots. The PCI IRQ routing are
according to Figure 5-2.
PowerQUICC II
DATA
SLOT
0
INTA A
SLOT
1
A
SLOT
2
A
ADDRESS
CONTROL
PCI
Interrupt
Controller
INTB B
INTC C
B
C
B
C
IRQ2
IRQ
INTD D
D
D
Figure 5-2. PCI Interrupt Routing Scheme
An interrupt request in any of the INTx lines, sets 3 interrupt bits i n the PCI interrupt
register (if not masked in the interrupt mask register) because every INTx line has three
possible interrupt sources. It is up to the user to implement a polling process to verify the
real interrupt source (by polling the interrupt pending bit in the PCI device) and clear the
other two. The PCI interrupt register can be read at any time and accessed at offset 0x0 from
CS3 base address. The description of the PCI interrupt register is in Table 5-3.
Table 5-3. PCI Interrupt Register Description
BI
T
0
MNEMONIC
PCI0_INTA
Function
PCI Slot 0 INTA . PCI Slot 0 Interrupt A:
PON
DEF
0
A
T
T.
R
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
1
PCI0_INTB
PCI Slot 0 INTB . PCI Slot 0 Interrupt B:
0
R
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
2
PCI0_INTC
PCI Slot 0 INTC . PCI Slot 0 Interrupt C:
0
R
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
3
PCI0_INTD
PCI Slot 0 INTD . PCI Slot 0 Interrupt D:
0
R
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
MPC8272ADS User Guide
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